The present invention relates to semiconductor integrated circuits such as single-chip microcomputers and digital signal processors which require distinction of the user mode from the mode used by the maker upon shipping.
Various operational modes of a single-chip microcomputer are shown in FIGS. 6(a), 6(b), and 6(c). The single-chip microcomputer 20 consists of a central processing unit 21 for performing arithmetic and logic operations; a random access memory 22 for temporarily storing data necessary for data processing; a read only memory 23 for storing in advance data such as programs necessary for data processing; a peripheral logic circuit 24; an input/output port 25; an operational mode control circuit 26 responsive to set operational mode control information to control gates between the CPU 21 and ROM 23, and data and address buses and control lines on a single chip.
In FIG. 6(a), a separate user logic circuit 27 is connected to the single-chip microcomputer 20 in the single chip mode. In this single chip mode, the microcomputer 20 controls the user logic 27 via the I/O port 25 and receives data from the user logic 27. The microcomputer 20 operates according to the program stored in the ROM 23.
In FIG. 6(b), an external memory 28 is connected to the single-chip computer 20 in the external memory mode. In this external memory mode, the external memory 28 is accessed for exchange of data on an address or data bus, or a few control lines via the specified I/O port 25. The program is stored in the external memory 28, and the ROM 23 is not used.
In FIG. 6(c), a tester 29 is connected to the single-chip microcomputer 20 in the module test mode. This module test mode is used by the microcomputer maker. Address data and control signals are fed to the single-chip microcomputer 20 from the tester 29 to operate the peripheral logic 24, ROM 23, and RAM 22 for testing the microcomputer 20. In the modes of FIGS. 6(a) and 6(b), the CPU 21 controls access to the peripheral logic 24, ROM 23, and RAM 22 but, in the module test mode of FIG. 6(c), the peripheral logic 24, ROM 23, and RAM 22 are tested by separating the CPU 21 from the internal buses of the microcomputer 20.
Respective timing charts of the single-chip mode in FIG. 6(a), the external memory mode in FIG. 6(b), and the module test mode in FIG. 6(c) are shown in FIGS. 7(a), 7(b), and 7(c). The I/O port 25 serves as a double function port through which address, data, and control signals are inputted and outputted in the modes other than single chip mode, where it operates as a simple port through which data is inputted and outputted by the program. In the external memory mode of FIG. 6(b), the microcomputer 20 outputs address and control signals while the data bus serves as an input/output. At this point, the value of the I/O port 25, which is outputted in FIG. 6(a), is no longer outputted. That is, the I/O port 25 functions as a simple bus buffer. In the module test mode of FIG. 6(c), the microcomputer 20 receives the address and control signals from the tester 29 while the data bus serves as an input/output. In this case, too, no value of the port latch is outputted.
A conventional operational mode control circuit 26a for setting the above operational modes is shown in FIG. 8. The operational mode register 41, which is composed of a register of one or more bits, stores operational mode control information for distinguishing the respective operational modes. A value is set in this register 41 by inputting a mode input value into the mode input terminal 47 which is dedicated to mode setting. A plurality of mode input terminals 47 may be provided, but the number of mode input terminals is reduced by providing a level decision circuit 42 into which three different levels 0 V, V.sub.cc, and 2 V.sub.cc (twice V.sub.cc) are inputted.
Another conventional operational mode control circuit 26b in a single-chip microcomputer is shown in FIG. 9. The operational mode register 51 is accessed from the data bus 59 via a path 61. The data bus 59 is interfaced with the outside via a port 58 which serves as a data bus buffer. The operational mode register 51 is made such that operational mode control information is set not only in response to the mode input level at the mode input terminal 57 (or the decision result of the level decision circuit 52) but also via the data bus 59.
The conventional semiconductor integrated circuit requires at least one mode input terminal dedicated to mode setting and has a disadvantage for single-chip microcomputers in which only a limited number of pins are available. In addition, as the number of operational modes increases, there is a demand for two or more mode input terminals.